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  1. the french mushroom (duponin@udongein.xyz)'s status on Sunday, 13-Feb-2022 22:42:00 CET the french mushroom the french mushroom
    reject x86
    embrace ARM
    In conversation Sunday, 13-Feb-2022 22:42:00 CET from udongein.xyz permalink
    • Ekaitz Zárraga 👹 (ekaitz_zarraga@mastodon.social)'s status on Sunday, 13-Feb-2022 22:42:00 CET Ekaitz Zárraga 👹 Ekaitz Zárraga 👹
      in reply to

      @duponin embrace RISC-V

      In conversation Sunday, 13-Feb-2022 22:42:00 CET permalink
    • the french mushroom (duponin@udongein.xyz)'s status on Sunday, 13-Feb-2022 22:43:43 CET the french mushroom the french mushroom
      in reply to
      • Ekaitz Zárraga 👹
      @ekaitz_zarraga isn’t RISC-V a subset of ARM?
      (please don’t burn my house and steal my cat, I’m an ignorant)
      In conversation Sunday, 13-Feb-2022 22:43:43 CET permalink
    • Ekaitz Zárraga 👹 (ekaitz_zarraga@mastodon.social)'s status on Sunday, 13-Feb-2022 22:44:15 CET Ekaitz Zárraga 👹 Ekaitz Zárraga 👹
      in reply to

      @duponin It's not.
      No real relation between them.

      In conversation Sunday, 13-Feb-2022 22:44:15 CET permalink
    • the french mushroom (duponin@udongein.xyz)'s status on Sunday, 13-Feb-2022 22:46:18 CET the french mushroom the french mushroom
      in reply to
      • Ekaitz Zárraga 👹
      @ekaitz_zarraga okay, I’m prob confused about something else

      didn’t you do a talk about RISC-V at FOSDEM 2022?
      In conversation Sunday, 13-Feb-2022 22:46:18 CET permalink
    • Ekaitz Zárraga 👹 (ekaitz_zarraga@mastodon.social)'s status on Sunday, 13-Feb-2022 22:46:57 CET Ekaitz Zárraga 👹 Ekaitz Zárraga 👹
      in reply to

      @duponin Not directly but yeah, I talked about some things we are doing on it. We are porting many things to RISC-V because it's kinda new.

      In conversation Sunday, 13-Feb-2022 22:46:57 CET permalink
    • Ekaitz Zárraga 👹 (ekaitz_zarraga@mastodon.social)'s status on Sunday, 13-Feb-2022 22:48:28 CET Ekaitz Zárraga 👹 Ekaitz Zárraga 👹
      in reply to

      @duponin Maybe that confuses you is the fact that both ARM and RISC-V are classified as RISC machines, meaning Reduced Instruction Set Computer, in contrast to CISC (complex blahblah blah) but that's just a design philosophy.
      The RISC-V and ARM standards are separate things.
      They have some similarities but just that.

      In conversation Sunday, 13-Feb-2022 22:48:28 CET permalink
    • the french mushroom (duponin@udongein.xyz)'s status on Sunday, 13-Feb-2022 22:52:14 CET the french mushroom the french mushroom
      in reply to
      • Ekaitz Zárraga 👹
      @ekaitz_zarraga nice
      do you have some resources to point me to? I’m teased and curious
      In conversation Sunday, 13-Feb-2022 22:52:14 CET permalink
    • Ekaitz Zárraga 👹 (ekaitz_zarraga@mastodon.social)'s status on Sunday, 13-Feb-2022 22:52:14 CET Ekaitz Zárraga 👹 Ekaitz Zárraga 👹
      in reply to

      @duponin wikipedia es ok for that kind of things. I don't have anything else for you. Maybe a book called "The RISC-V reader: an open architecture atlas". But it's pretty detailed about the architecture itself.
      The interesting thing of RISC-V is it's an open standard and you don't need to pay royalties for using it (in ARM you have to).

      In conversation Sunday, 13-Feb-2022 22:52:14 CET permalink

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