s-ol
I think the correct syntax for the Sub-V label-reference immediates (and similar ones) will be one of:
label+4/offlabel+4/off13label+4/off13/[12:1]
(from less to more verbose, with format.py filling in the gaps based on knowledge of the instruction)
The "+4" is a variable offset that can be omitted when unused also.
s-ol
The thing that I am still undecided on is how to handle e.g. AUIPC+JALR here with respect to range-checking. My general idea would be that writing
label+4/off13/[12:1]
will cause an error if "label+4" doesn't fit in a 13-bit signed number. But when a AUIPC+JALR combo is used, the JALR instruction immediate should be a "sign-compressed" slice of the 32 bit complete offset.
s-ol
I wanted to avoid having a separate syntax for that, but I think it might be necessary to add
label+4/off32/[:11:1]
where the extra ":" says to copy the sign bit in addition to the given slice.
When only
label+4/off
is specified, this kind of truncated 32 bit offset could also be used automatically on relevant instructions (maybe that's only JALR, I haven't even looked at most branches yet)
s-ol
@akkartik @ekaitz_zarraga I bet this is hard to follow, but does this make sense to either of you by any chance?
s-ol
@akkartik @ekaitz_zarragamaybe instead of [:H:L] it should be [1:H:L] which can be read as "one sign bit, then all the bits from H to L, inclusive" and also it aligns somewhat better with python syntax
s-ol
@ekaitz_zarraga @akkartik The 1 would be either 1 or 0 in other contexts, but when it is 0 it would probably be left off. I think putting a literal 1 there is nice because it makes it more obvious that it takes up a bit:
size([H:L]) = (H - L) + 1size([1:H:L]) = 1 + (H - L) + 1
(the +1 is because bit-slice indices are inclusive)
s-ol
@ekaitz_zarraga @akkartik hm, the +1 / inclusive ranging is not from python actually, I took that from Verilog and VHDL.
In python, slicing is [inclusive:exclusive], e.g.:
>>> a = [0,1,2,3]>>> a[0:3][0, 1, 2]
I guess for bits this would be flipped, so to take the lower 8 bit of a larger number (bits 7, 6, 5, 4, 3, 2, 1, and 0):
num[8:0]
s-ol
ok, i'm still a bit conflicted on this, but maybe this is actually cleaner?It's tricky because I don't think there is a good natural intuition for this, so it mostly depends on how you are used to this off-by-one thing behaving in other contexts. But I definitely like that this is much clearer to read as a size.
Kartik Agaram
@s_ol The basics make sense, though I don't understand the sign bit. Is the instruction grabbing 11 LSBs and 1 MSB?
The slicing operators seem find, but I'm not sure how I feel about the `label+4` syntax. One heuristic I used in SubX was to not try to use all the available power of the instruction set. Are you sure you need far jumps to unaligned addresses? Maybe organize code in pages, with cross-page jumps restricted to the start. A dispatch table or something.
s-ol
@akkartikAs for the last part, I could not implement JALR or cripple it to do only absolute jumps, but the RISC-V ISA is already so lean and it is closely in reach so it feels like a bit of a shame IMO.
I think it would be especially interesting to have a fully capable machine code language for RISC-V because the canon assembler already does a lot of lifting with pseudoinstructions (especially for jumps) so SubV could be very educational there.
Kartik Agaram
@s_ol I think I see the constraints now.
A pseudoinstruction might be an option. Represent auipc+jalr altogether, and mention the label just once.
This whole RISC-V feature makes me nervous. Are there any special boundaries where auipc being on one side and jalr being on the other would lead to subtle problems?
Can you -1 more in auipc and keep offset positive?
CISC looks pretty good right now 🙂
You haven't really said anything about your goals? I get the sense they're different from mine.
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