Notices

1. Vertigo #$FF (vertigo@hackers.town)'s status on Monday, 28-Jun-2021 23:29:24 CEST Vertigo #$FF

   in reply to

   Always known that commercial FPGA/ASIC developer tools are, well, shit. Like, this stuff is irreparably bad.

   But, the extent to which Synopsis and Cadence tools suck can best be summarized as threatening to civilization itself. The time dilation engineers go through when working with these pieces of shit is so extensive that they'd make ideal case studies for black hole research.

   "Oh, I'll just get this design working on the simulation environment, and, holy shit, it's already next week! What the fuck just happened?!"

   I haven't even finished this week out, and I'm already so fucking done working with this bullshit.

   I really wish I had the economic freedom to demand, "Give me Yosys and Verilator, or give me a pink slip."

   • Vertigo #$FF (vertigo@hackers.town)'s status on Monday, 28-Jun-2021 23:29:25 CEST Vertigo #$FF

     I'd much rather be streaming me coding in Z80 assembly language right about now. Sigh.

     Ekaitz Zárraga 👹 repeated this.