@ekaitz_zarraga yo al ser gallego 100% he acabado emigrado por Finlandia, que habrá que ayudar a mantener el estereotipo 😅

@ekaitz_zarraga ciertamente, no era complicado de imahinar, jeje. En todo caso, que viva el norte!

@ekaitz_zarraga wow, amusingly the original English version of the book is a paid one, while the translation is freely downloadable. Now that's unexpected :thaenkin:

@ekaitz_zarraga sounds like a good reason, I was suspecting something like that, actually.

@ekaitz_zarraga thanks!

En efecto, soy del noroeste peninsular ⛵🏴☠️

@ekaitz_zarraga yes, it looked great from a quick look I took a while ago, and I'm really looking forward to summer holidays to start playing a bit, maybe with Tinyemu at first because the Nezha will take a while to arrive. I do have a vague memory of some kinds of instructions in RISC-V having a bit of a wonky encoding, but I expect it to have a good reason. Anyway, it's not like one usually writes e.g. an assembler and at that level some more bit twiddling doesn't really matter much.

Hot take: MIPS has the most orthogonal and approachable instruction set around.

At least of we were ave RISC-V out. I may need to reevaluate that statement once I start poking around.

No idea what I'll be doing with it. One possible project would be porting the JavaScriptCore JIT, but sounds too daunting. Something funnier could be some bare metal programming, because the learning curve should build okay given that I can write MIPS assembler already and RISC-V is a somewhat direct descendant...

Welp, I may have accidentally a RISC-V Nezha board.

@mntmn do I understand correctly that this would allow for example putting a bitstream for a RISC-V core in the FPGA, and then having that as the main CPU for the Reform? If yes, that would be extremely cool, and I can already imagine people doing awesome stuff like “hey, this Reform is actually a MSX/Spectrum/Amiga/whatever laptop” :blobaww: